RCC workshops: Three workshops on parallel programming from Intel
The Research Computing Center will be hosting three workshops on parallel programming from Intel during the month of May. All workshops will be held in the Kathleen A. Zar Room in the John Crerar Library. More information on the workshop topics, as well as registration links, are available in the workshop descriptions below:
Intel Software for High-Performance Parallel Applications
Wednesday, May 20, 2015, 9:00 a.m. to 5:00 p.m. | Kathleen A. Zar Room, John Crerar Library
In this workshop, you will be introduced to Intel Parallel Studio XE Cluster Edition, a multi-component software toolkit to create parallel applications, with a focus on trace collection and analysis. You will also be introduced to Intel compilers, along with Intel’s performance and threading analysis tools, such as Intel VTune Amplifier, Intel Inspector, and Intel Advisor. Finally, you will be introduced to the Intel Math Kernel Library, a math library specially designed for high performance on Intel processors.
Register for this workshop here.
Parallel Programming and Optimization with Intel Xeon Phi Coprocessors: CDT 101
Thursday, May 21, 2015, 9:30 a.m. to 4:30 p.m. | Kathleen A. Zar Room, John Crerar Library
This one-day training provides software developers the foundation needed for modernizing their codes to extract more of the parallel compute performance potential found in both Intel Xeon processors and Intel Xeon Phi coprocessors.
The session will cover:
- Intel Xeon Phi architecture: purpose, organization, pre-requisites for good performance, future technology
- Programming models: native, offload, heterogeneous clustering
- Parallel frameworks: automatic vectorization, OpenMP, MPI
- Optimization methods: general, scalar math, vectorization, multithreading, memory access, communication and special topics
Register for this workshop here.
Parallel Programming and Optimization with Intel Xeon Phi Coprocessors: CDT 102
Friday, May 22, 2015, 9:30 to 4:30 p.m. | Kathleen A. Zar Room, John Crerar Library
This one-day training provides software developers the foundation needed for modernizing their codes to extract more of the parallel compute performance potential found in both Intel Xeon processors and Intel Xeon Phi coprocessors. It builds on information attendees will have learned in the previous day’s workshop, CDT 101.
The session will cover:
- Intel Xeon Phi architecture: purpose, organization, pre-requisites for good performance, future technology
- Programming models: native, offload, heterogeneous clustering
- Parallel frameworks: automatic vectorization, OpenMP, MPI
- Optimization methods: general, scalar math, vectorization, multithreading, memory access, communication and special topics
Please note: You must complete CDT 101 before taking CDT 102.
